A voltage-controlled oscillator, where the oscillation frequency changes as a function of the control voltage, then creates the output clock. Through negative feedback, the control signal forces the output clock phase to be aligned with the input clock phase, resulting in zero phase error.Like the PLL, a DLL can also provide an accurate timing relationship between an input clock and output clock. Therefore, it is also a viable option for clock generation in a high-speed link. A DLL utilizes a voltage-controlled delay line to generate an output clock that is a delayed version of the input clock, where the delay through the VCDL is a fixed fraction of the input clock period. While there are several ways to implement a DLL, Fig. 2.3 presents a block diagram of a commonly-used charge pump based DLL topology. A phase detector measures the phase difference between coincident edges of the input and output clocks of the VCDL. The charge pump generates pulses of charge, proportional to the phase error, which is then integrated by the capacitor in the loop filter . The resulting voltage out of the LF sets the magnitude of the control voltage that determines the delay through the VCDL. Since the reference clock also feeds into the input of the VCDL,drying weed delay through the VCDL is fixed with respect to the period of reference through negative feedback. A DLL is inherently simpler and easier to stabilize than a PLL. The VCO in a PLL must change frequency in order to adjust its output phase, introducing an integrator.
In comparison, the phase of the clock edge out of the VCDL is directly controlled by Vctrl, which corresponds to a simple gain without integration. Hence, a DLL can be designed as a first-order loop and obviates adding proportional control to stabilize the loop. Moreover, frequency detection is not needed since the input and output clocks nominally have the same frequency. DLL is better modeled by a discrete time z-domain because of the presence of a delay line that produces 1 clock cycle delay. A continuous time model can capture the delay effect but it ignores the impact of this delay on the sampling nature of the loop and its dynamics. Fig. 2.4 shows the z-domain model of the DLL. Kvcdl is the delay line gain in radians per cycle per volt. LF is the loop filter transfer function. After combining the phase correction term with the input reference clock phase, a one-cycle delay is applied. Supply noise modulates the delay of the VCDL and its effects are modeled by simply adding a noise term, Nout, before the output node.Similar to the PLL, the DLL output noise transfer function also has a high-pass characteristic, similar to that seen for a PLL. The high-pass corner frequency corresponds to the bandwidth of the loop. While the NTF responses of both the PLL and DLL are similar, there is an important distinction to point out. In a PLL, the output phase can only move by changing the VCO frequency, while in a DLL, the loop can directly move the output phase by adjusting the delay through the VCDL. This difference enables the DLL to respond much more quickly to noise injected at the output.
Moreover, power supply noise is a dominant source of noise that must be dealt with in order to achieve low jitter. The VCDL used in a DLL has the added advantage of not accumulating the noise, as opposed to the VCO in a PLL. Therefore, power-supply noise that may couple into the VCDL only affects the output phase over a single clock period. Fig. 2.5 shows the transfer functions of the PLL and the DLL for different bandwidth settings. As seen from the plot, the DLL transfer function is all-pass, peaking is observed in the transfer function with increase in bandwidth. The peaking can be reduced by increasing the DLL filter order [19]. The PLL is thus adequate when noise is dominated by clock input noise as the PLL low pass filters this noise, while the DLL is more adequate for systems that have clean input clocks and noisy supply and substrates because the DLL VCDL doesn’t accumulate supply noise as the VCO inside the PLL does. Re-aligned PLL is another approach to clean up the accumulated VCO-induced jitter periodically. The topology performs VCO phase realignment by injection locking the VCO to a strongly buffered version of the PLL reference clock at fixed intervals of the reference clock. Fig. 2.6 presents a block diagram of this topology. A buffered version of reference clock is injected into one of the delay cells in the VCO every reference cycle to pull the VCO internal clock edge toward the ideal position. If the amount of phase error correction is big enough to correct the phase difference between the buffered reference and the internal clock edge prior to the realignment, all the memory of the past errors at the VCO output clock can be completely suppressed.
If the reference clock is clean, the accumulated noise in the VCO can be suppressed by resetting the accumulated phase error; thus, improving the supply noise rejection of the RPLL by realignment. The relative strength of the injection locking buffer to the delay cells in the VCO determines the amount of phase realignment performed. The injection operation is synchronized by a SEL pulse that is derived from the VCO output clock. The main drawback in this topology stems when there is a difference in delay through the reference clock injecting buffer versus the VCO buffers the injection can create a phase mismatch between the reference clock edge and the output edge out of the VCO. This can lead to pattern jitter at the VCO output set by the periodicity of injection. This corresponds to a strong injection-induced spur when observing the spectrum of the output clock. A solution to resolve this problem will be proposed in chapter 4. The topology can be extended to multiply the input clock by adding a divider in the feedback path, which gives the circuit the name “Multiplying DLL” or . The MDLL loop dynamics are similar to the DLL. This is because the injection happens at the reference frequency rate which makes the MDLL behaves as an DLL running at the reference frequency, while the VCO integration happens at the multiplied frequency in an open loop manner. Time jitter is a key measurement in systems where the periodic behavior or exact event timing is crucial to system performance. The design process for high performance, low cost devices in today’s communication systems requires comprehensive methods for modeling and analyzing both jitter and noise. Jitter measures undesired fluctuations in the timing of events; In oscillators and frequency synthesizers period jitter quantifies the time domain uncertainty of the output signal. In digital design period jitter describes the misalignment of the significant edges of a digital signal from their ideal position in time. In communication systems, “jitter is an abrupt and unwanted variation of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles or the frequency or phase of successive cycles”. The clock path repeater is shown in Fig. 3.1. The clock is first amplified in a 100Ω terminated 3-stage differential receiver followed by a limiting amplifier that produces digital levels. The CMU input is fed from CMOS buffers. Output of the amplified clock and a divided version of the CMU are inputs to a phase interpolator. The role of this phase interpolator as a filter is discussed in subsequent sections. A clock driver sends the clock to the next cable section. This work uses a differential wire pair for sending the clock.Alternatively,vertical growing systems the clock can be sent embedded as the common-mode component of differential data lines. Power for each data or clock repeater is provided through the cable.
Many standards include wires for power with well-defined maximum voltage and current. Infiniband,HDMI, and Thunderbolt are a few examples of standards. The two wires for power can also be reduced by combining the clock and power wires by launching the power across signal lines as in Power over Ethernet applications. Clock doesn’t need equalization and clock frequency can be chosen arbitrarily provided that we have a clock multiplication unit in each repeater. Hence, clock repeating distance need not be the same as the data repeating distance. Practically, clock path needs less repeaters than data path. As seen from Fig. 1.2, clock is dropped-off at each data repeating stage for frequency multiplication, if needed, and retiming, while it’s repeated only each clock repeating distance. The incoming clock signal is amplified through the cascade of repeater gain stages. Depending on its amplitude, the clock amplitude saturates within few stages. The gain then drops to almost unity throughout the remain gain stages. For that reason, noise propagation inside the clock repeater can’t be modeled with the traditional linear time invariant model, even though noise is still considered small signal. Instead, the problem needs to be solved using a time-variant linear model. Many modern circuit simulators can simulate and solve circuits using this model. The periodic nature of the clock permits these tools to solve for a time varying DC operating point. At those time varying operating points, the circuit can be linearized and a time-variant transfer function H can be obtained, where t is the observation time. Fig. 3.2 exemplifies this case for a gain stage driven out of its linear operation with a strong input signal. The gain stage can still be linearized around its DC operating point. The previous discussion suggests that the amplitude and slew rate of the clock signal affect the transfer function of the clock repeater and the noise. Fig. 3.3 plots total gain and noise accumulation inside the clock repeater for 2 cases; A small clock amplitude and a large clock amplitude . Both clock signals result in the same amplitude and slew rate at the output of the repeater. The small clock amplitude undergoes high and linear gain at the first few stages. Gain eventually compresses. A linear time variant analysis shows the time-averaged gain drops to one at the 4th stage onward. Noise contribution from earlier stages dominates total noise. Noise contribution of last stages is minimal due to diminished gain and large clock slew rate. For the large clock amplitude, the average gain is even less than one early on the clock chain. Simply because the applied clock has much higher slew rate than the gain stages max slew rate during clock transition, while it’s saturated elsewhere in the clock cycle. This results in less than unity time-averaged gain. Starting from the 4th stage, the stage gain becomes unity. Noise growth is noticeably limited due to the reduced gain, and the result is that integrated noise of a small clock amplitude is twice as large as for large swing clock. It’s to be noted also that the slight drop in integrated noise at stages 7 and 8 is attributed to reduction in noise bandwidth as we approach the end of the repeater. Fig. 3.4 shows the impact of the slew rate on the total noise power of a 70mV clock amplitude. As input slew rate increases, stages saturate earlier, their gain drops and so does noise contribution. Overlaid in Fig. 3.4 is the noise power for 1st and 2nd repeater stages. They represent almost 80% of total repeater noise. Also overlaid on figure is noise power estimate based on LTV gain from equation and noise sources calculated from devices in 1st and 2nd repeater stages. To evaluate jitter at the output of the clock repeater. Noise needs to be evaluated at the zero crossing instance t0. As we mentioned earlier, the LTV transfer function in can be used to evaluate root mean square noise at the output of the repeater at different time points. Fig. 3.5 shows the clock repeater output noise and clock amplitude calculated with SpectreRF periodic steady state time domain noise , Which uses to evaluate noise at different time points. The graph shows the noise voltage at zero crossing point equals 12.5mVrms. It also shows that average noise voltage is only 2mVrms.